1. Technical Field
The present invention relates to an electroless surface treatment plated layer of a printed circuit board, a method for preparing the same, and a printed circuit board including the same.
2. Description of the Related Art
In accordance with an increase in density of an electronic component, various technologies regarding surface treatment of a printed circuit board (PCB) have been developed. In accordance with the recent demand of PCB products that have been thinned and densified, a process of treating a surface of the PCB has been recently changed from electro Ni/Au surface treatment into electroless surface treatment in which tailless implementation may be easily performed in order to simplify a process and solve a problem such as noise, or the like.
Particularly, since the existing used electroless Ni/Au (hereinafter, referred to as ENIG) and recently prominent electroless Ni/Pd/Au (hereinafter, referred to as ENEPIG) have excellent solder connection reliability and wire bonding reliability, they have been used in various fields as well as a package substrate. However, in accordance with miniaturization of a wiring for increasing density of the electronic component, problems of a technology of surface-treating the circuit board according to the related art have started to emerge.
Meanwhile, as a scheme of connecting various devices such as a die, a main board, and the like, to each other, there are mainly two schemes, that is, a wire-bonding scheme and a solder joint scheme.
FIGS. 1A and 1B are, respectively, a cross-sectional view and a top view when a plated layer and a device are connected to each other using the wire-bonding scheme according to the related art. Referring to FIGS. 1A and 1B, a polymer resin layer 20 is first formed at a portion except for a copper layer 10 in a printed circuit board to thereby subsequently serve as a resist to plating, and electroless Ni layer 31/Pd layer 32/Au layer 33 are formed as a plated layer 30 using an electroless plating method in order to protect the copper layer 10. In addition, after the electroless Ni/Pd/Au surface treatment plated layer 30 is formed, the metal layers are interconnected using a gold (Au) wire, or the like.
In a substrate including the plated layer 30 of the ENIG or ENEPIG, in the case of the ENIG, the Ni layer has a thickness of at least 3 μm and the Au layer has a thickness of 0.05 to 0.5 μm, and in the case of the ENEPIG, the Ni layer has a thickness of at least 3 μm, the Pd layer has a thickness of 0.05 to 0.3 μm, and the Au layer has a thickness of 0.05 to 0.5 μm, as seen in FIG. 2.
That is, the Ni layer generally has the thickest thickness of 3 μmor more, more specifically, 3 to 7 μm. The reason is that the electroless Ni layer needs to have coating performance without a defect in order to serve as a barrier layer to thereby suppress diffusion of underlying copper.
However, when the thickness of the Ni layer is thick, as a frequency increases, a phenomenon in which a current flows in a surface due to a skin effect, such that it is concentrated on an outermost layer of Ni/Au or Ni/Pd/Au rather than an inner layer of Cu wiring occurs. However, the Ni layer has electrical resistance higher than that of CU, such that electrical characteristics are deteriorated. Therefore, a solution thereof has been demanded.
Further, in the case in which the layers have the above-mentioned thicknesses, it is impossible to reduce a space between patterns to 25 μm or less, which is an object of the next generation technology. The reason is that when the space between the patterns becomes narrow, the Ni layer abnormally grows between the patterns to thereby cause an electrical bridge.